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White Electronic Designs
WME128K8-XXX
128Kx8 CMOS MONOLITHIC EEPROM, SMD 5962-96796
FEATURES
Read Access Times of 120, 140, 150, 200, 250, 300ns JEDEC Approved Packages * 32 pin, Hermetic Ceramic, 0.600" DIP (Package 300) * 32 lead, Hermetic Ceramic, 0.400" SOJ (Package 101) Commercial, Industrial and Military Temperature Ranges MIL-STD-883 Compliant Devices Available Write Endurance 10,000 Cycles Data Retention at 25C, 10 Years Low Power CMOS Operation Automatic Page Write Operation * Internal Address and Data Latches for 128 Bytes * Internal Control Timer Page Write Cycle Time 10ms Max. Data Polling for End of Write Detection Hardware and Software Data Protection TTL Compatible Inputs and Outputs
This product is subject to change without notice.
FIGURE 1 -
Pin Configuration 32 DIP 32 CSOJ Top View
NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
Pin Description
A0-16 I/O0-7 CS# OE# WE# VCC VSS Address Inputs Data Input/Output Chip Selects Output Enable Write Enable +5.0v Power Ground
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC WE# NC A14 A13 A8 A9 A11 OE# A10 CS# I/O7 I/O6 I/O5 I/O4 I/O3
White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2004 Rev. 5 January 2004 Rev. 5 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter Operating Temperature Storage Temperature Signal Voltage Relative to GND Voltage on OE# and A9 Symbol TA TSTG VG -55 to +125 -65 to +150 -0.6 to + 6.25 -0.6 to +13.5 Unit C C V V CS# H L L X X X OE# X L H H X L WE# X H L X H X
WME128K8-XXX
TRUTH TABLE
Mode Standby Read Write Out Disable Write Inhibit Data I/O High Z Data Out Data In High Z/Data Out
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAPACITANCE
TA = +25C Parameter Input Capacitance Output Capacitance Symbol CIN COUT Conditions VIN = 0 V, f = 1MHz VI/O = 0 V, f = 1MHz Max Unit 20 pF 20 pF
RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage Input High Voltage Input Low Voltage Operating Temp. (Mil.) Operating Temp. (Ind.) Symbol VCC VIH VIL TA TA Min 4.5 2.0 -0.5 -55 -40 Max 5.5 VCC + 0.3 +0.8 +125 +85 Unit V V V C C
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55C TA +125C Parameter Input Leakage Current Output Leakage Current Operating Supply Current Standby Current Output Low Voltage Output High Voltage Symbol ILI ILO ICC ISB VOL VOH Conditions VCC = 5.5, VIN = GND to VCC CS# = VIH, OE# = VIH, VOUT = GND to VCC CS# = VIL, OE# = VIH, f = 5MHz, VCC = 5.5 CS# = VIH, OE# = VIH, f = 5MHz, VCC = 5.5 IOL = 2.1mA, VCC = 4.5V IOH = -400A, VCC = 4.5V Min Max 10 10 80 0.625 0.45 Unit A A mA mA V V
2.4
NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V
FIGURE 2 - AC Test Circuit
Current Source
AC TEST CONDITIONS
IOL
D.U.T Ceff = 50 pf
Vz ~ 1.5V ~ Bipolar Supply
Parameter Input Pulse Levels Input Rise and Fall Input and Output Reference Level Output Timing Reference Level
Typ VIL = 0, VIH = 3.0 5 1.5 1.5
Unit V ns V V
Current Source
IOH
Notes: VZ is programmable from -2V to +7V. IOL & IOH programmable from 0 to 16mA. Tester Impedance Z0 = 75. VZ is typically the midpoint of VOH and VOL. IOL & IOH are adjusted to simulate a typical resistive load circuit. ATE tester includes jig capacitance.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2004 Rev. 5 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
READ
Figure 3 shows Read cycle waveforms. A read cycle begins with selection address, chip select and output enable. Chip select is accomplished by placing the CS# line low. Output enable is done by placing the OE# line low. The memory places the selected data byte on I/O0 through I/O7 after the access time. The output of the memory is placed in a high impedance state shortly after either the OE# line or CS# line is returned to a high level.
WME128K8-XXX
FIGURE 3 - READ WAVEFORMS
t RC ADDRESS
ADDRESS VALID
CS# t ACS OE# t ACC OUTPUT
HIGH Z
t OE t DF t OH
OUTPUT VALID
NOTE: OE# may be delayed up to tACS- tOE after the falling edge of CS# without impact on tOE or by tACC- tOE after an address change without impact on tACC.
AC READ CHARACTERISTICS (See Figure 3)
VCC = 5.0V, VSS = 0V, -55C TA +125C Read Cycle Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Hold from Address Change, OE# or CS# Output Enable to Output Valid Chip Select or OE# to High Z Output Symbol tRC tACC tACS tOH tOE tDF -120 Min 120 Max 120 120 0 0 50 60 0 0 -140 Min 140 Max 140 140 55 70 0 0 -150 Min 150 Max 150 150 55 70 0 0 -200 Min 200 Max 200 200 55 70 0 0 -250 Min 250 Max 250 250 85 70 0 0 -300 Min 300 Max 300 300 85 70 Unit ns ns ns ns ns ns
White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2004 Rev. 5 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WRITE
Write operations are initiated when both CS# and WE# are low and OE# is high. The EEPROM devices support both a CS# and WE# controlled write cycle. The address is latched by the falling edge of either CS# or WE#, whichever occurs last. The data is latched internally by the rising edge of either CS# or WE#, whichever occurs first. A byte write operation will automatically continue to completion.
WME128K8-XXX
WRITE CYCLE TIMING
Figures 4 and 5 show the write cycle timing relationships. A write cycle begins with address application, write enable and chip select. Chip select is accomplished by placing the CS# line low. Write enable consists of setting the WE# line low. The write cycle begins when the last of either CS# or WE# goes low. The WE# line transition from high to low also initiates an internal 150sec delay timer to permit page mode operation. Each subsequent WE# transition from high to low that occurs before the completion of the 150sec time out will restart the timer from zero. The operation of the timer is the same as a retriggerable one-shot.
AC WRITE CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55C TA +125C 128Kx8 Parameter Write Cycle Time, TYP = 6ms Address Set-up Time Write Pulse Width (WE# or CS#) Chip Select Set-up Time Address Hold Time Data Hold Time Chip Select Hold Time Data Set-up Time Output Enable Set-up Time Output Enable Hold Time Write Pulse Width High Symbol Min tWC tAS tWP tCS tAH tDH tCH tDS tOES tOEH tWPH 10 100 0 100 10 0 50 0 0 50 Max 10 ms ns ns ns ns ns ns ns ns ns ns Unit
White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2004 Rev. 5 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WME128K8-XXX
FIGURE 4 - WRITE WAVEFORMS WE# CONTROLLED
t WC OE# t OES ADDRESS t AS CS# t CS WE# t WP t DS DATA IN t WPH t DH t AH tCSH t OEH
FIGURE 5 - WRITE WAVEFORMS CS# CONTROLLED
t WC OE# t OES ADDRESS t AS WE# t CS CS# t WP t DS DATA IN t WPH t DH t AH tCSH t OEH
White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2004 Rev. 5 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
DATA POLLING
The WME128K8-XXX offers a data polling feature which allows a faster method of writing to the device. Figure 6 shows the timing diagram for this function. During a byte or page write cycle, an attempted read of the last byte written will result in the complement of the written data on I/O7. Once the write cycle has been completed, true data is valid on all outputs and the next cycle may begin. Data polling may begin at any time during the write cycle.
WME128K8-XXX
DATA POLLING CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55C TA +125C Parameter Data Hold Time OE# Hold Time OE# To Output Valid Write Recovery Time Symbol tdh toeh toe twr Min 10 10 0 Max Unit ns ns ns ns
55
FIGURE 6 - DATA POLLING WAVEFORMS
WE#
CS# t OEH OE# t DH t OE HIGH Z t WR ADDRESS
I/O7
TOGGLE BIT: In addition to DATA# Polling another method for determining the end of a write cycle is provided . During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle.
TOGGLE BUT CHARACTERISTICS(1)
Symbol tDH tOEH tOE tOEHP tWR Parameter Data Hold Time OE Hold Time OE to Output Delay OE High Pulse Write Recovery Time Min 10 10 150 0 Max Units ns ns ns ns ns
WE# CS# tOEH OE# tDH I/O6
(2)
tOE
HIGH Z tWR
NOTE: 1. Toggling either OE# or CS# or both OE# and CS# will operate toggle bit. 2. Beginning and ending state of I/O6 will vary 3. Any address location may be used but the address should not vary.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2004 Rev. 5 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
PAGE WRITE OPERATION
The WME128K8-XXX has a page write operation that allows one to 128 bytes of data to be written into the device and consecutively loads during the internal programming period. Successive bytes may be loaded in the same manner after the first data byte has been loaded. An internal timer begins a time out operation at each write cycle. If another write cycle is completed within 150s or less, a new time out period begins. Each write cycle restarts the delay period. The write cycles can be continued as long as the interval is less than the time out period. The usual procedure is to increment the least significant address lines from A0 through A6 at each write cycle. In this manner a page of up to 128 bytes can be loaded in to the EEPROM in a burst mode before beginning the relatively long interval programming cycle. After the 150s time out is completed, the EEPROM begins an internal write cycle. During this cycle the entire page of bytes will be written at the same time. The internal programming cycle is the same regardless of the number of bytes accessed.
WME128K8-XXX
PAGE WRITE CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55C TA +125C Page Mode Write Characteristics Parameter Write Cycle Time, TYP = 6ms Address Set-up Time Address Hold Time (1) Data Set-up Time Data Hold Time Write Pulse Width Byte Load Cycle Time Write Pulse Width High Symbol Min twc tas tah tds tdh twp tblc twph 10 100 50 10 100 150 50 Max 10 Unit ms ns ns ns ns ns s ns
1. Page address must remain valid for duration of write cycle.
FIGURE 7 - PAGE MODE WRITE WAVEFORMS
OE#
CS#
t WP WE#
t WPH
t BLC
t AS ADDRESS
VALID ADDRESS
t AH
t DS DATA
t DH
BYTE 0 BYTE 1 BYTE 2 BYTE 3
t WC
BYTE 127
VALID DATA
White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2004 Rev. 5 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
WME128K8-XXX
FIGURE 8 - SOFTWARE DATA PROTECTION ENABLE ALGORITHM(1)
LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE TO LAST ADDRESS ENTER DATA PROTECT STATE WRITES ENABLED(2)
NOTES: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A16 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data to be loaded.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2004 Rev. 5 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
FIGURE 9 - SOFTWARE BLOCK DATA PROTECTION DISABLE ALGORITHM(1)
WME128K8-XXX
SOFTWARE DATA PROTECTION
A software write protection feature may be enabled or disabled by the user. When shipped by White Microelectronics, the WME128K8-XXX has the feature disabled. Write access to the device is unrestricted. To enable software write protection, the user writes three access code bytes to three special internal locations. Once write protection has been enabled, each write to the EEPROM must use the same three byte write sequence to permit writing. After setting software Data protection, any attempt to write to the device without the three-byte command sequence will start the internal write timers. No Data will be written to the device; however, for the duration of tWC. The write protection feature can be disabled by a six byte write sequence of specific data to specific locations. Power transitions will not reset the software write protection. The software write protection guards against inadvertent writes during power transitions or unauthorized modification using a PROM programmer.
LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 20 TO ADDRESS 5555 LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE TO LAST ADDRESS
HARDWARE DATA PROTECTION
EXIT DATA PROTECT STATE(3)
These features protect against inadvertent writes to the WME128K8-XXX. These are included to improve reliability during normal operation: a) VCC power on delay As VCC climbs past 3.8V typical the device will wait 5msec typical before allowing write cycles. b) c) VCC sense While below 3.8V typical write cycles are inhibited. Write inhibiting Holding OE# low and either CS# or WE# high inhibits write cycles. d) Noise filter Pulses of <15ns (typ) on WE# or CS# will not initiate a write cycle.
NOTES: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A16 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data may be loaded.
White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2004 Rev. 5 9 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
PACKAGE 101: 32 LEAD, CERAMIC SOJ
WME128K8-XXX
21.1 (0.830) 0.25 (0.010) 0.2 (0.008) 0.05 (0.002)
3.96 (0.156) MAX 0.89 (0.035) Radius TYP
11.3 (0.446) 0.2 (0.009)
9.55 (0.376) 0.25 (0.010)
1.27 (0.050) 0.25 (0.010)
PIN 1 IDENTIFIER 1.27 (0.050) TYP 19.1 (0.750) TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE 300: 32 PIN, CERAMIC DIP, SINGLE CAVITY SIDE BRAZED
42.4 (1.670) 0.4 (0.016) 15.04 (0.592) 0.3 (0.012) 4.34 (0.171) 0.79 (0.031)
PIN 1 IDENTIFIER
0.84 (0.033) 0.4 (0.014)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2004 Rev. 5 10 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
ORDERING INFORMATION
W M E 128K8 - XXX X X X
LEAD FINISH: Blank = Gold plated leads A = Solder dip leads
WME128K8-XXX
DEVICE GRADE: Q = MIL-STD-883 Compliant M = Military Screened -55C to +125C I = Industrial -40C to +85C C = Commercial 0C to +70C PACKAGE TYPE: C = 32 Pin Ceramic DIP (Package 300) DE = 32 Lead CSOJ (Package 101) ACCESS TIME (ns) ORGANIZATION 128K x 8 EEPROM MONOLITHIC WHITE ELECTRONIC DESIGNS CORP.
DEVICE TYPE
128K x 8 EEPROM Monolithic 128K x 8 EEPROM Monolithic 128K x 8 EEPROM Monolithic 128K x 8 EEPROM Monolithic 128K x 8 EEPROM Monolithic 128K x 8 EEPROM Monolithic
SPEED
300ns 250ns 200ns 150ns 140ns 120ns
PACKAGE
32 pin DIP (C) 32 pin DIP (C) 32 pin DIP (C) 32 pin DIP (C) 32 pin DIP (C) 32 pin DIP (C)
SMD NO.
5962-96796 01HYX 5962-96796 02HYX 5962-96796 03HYX 5962-96796 04HYX 5962-96796 05HYX 5962-96796 06HYX
128K x 8 EEPROM Monolithic 128K x 8 EEPROM Monolithic 128K x 8 EEPROM Monolithic 128K x 8 EEPROM Monolithic 128K x 8 EEPROM Monolithic 128K x 8 EEPROM Monolithic
300ns 250ns 200ns 150ns 140ns 120ns
32 lead SOJ (DE) 32 lead SOJ (DE) 32 lead SOJ (DE) 32 lead SOJ (DE) 32 lead SOJ (DE) 32 lead SOJ (DE)
5962-96796 01HXX 5962-96796 02HXX 5962-96796 03HXX 5962-96796 04HXX 5962-96796 05HXX 5962-96796 06HXX
White Electronic Designs Corp. reserves the right to change products or specifications without notice. January 2004 Rev. 5 11 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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